RISC AND CISC
In broader terms, computers can be divided into two components- hardware and software. For architecture designing , both components play a major role. So, the architecture designing of CPU depends on two computing designs:- CISC(Complex Instruction Set Computer) and RISC(Reduced Instruction Set Computer).
Before discussing CISC and RISC architectures, there are certain concepts , which should be known. These are :-
- Instruction Set– It is formed by a group of instructions to execute a program. This set is formed by opcode and operand. Opcode is the instruction (e.g. Load, store) and Operand is the memory register to which this instruction is applied.
- Addressing Modes- Addressing modes define the ways in which the data is accessed. Data can be accessed in two ways. One is direct mode where in data is directly accessed. Another is Indirect mode wherein, data is accessed by its location.
- Semantic gap- This signifies the difference between the machine-level instructions a computer could execute, and the high-level language that would be compiled to execute them.
CPU performance is dependent upon various factors like Instruction count, Cycles per Instruction(CPI) and Clock cycle time. Every designing architecture underlines the importance of CPU performance. This is the main concern to achieve while designing. And all these three factors are affected by the Instruction Set architecture.
- CISC architecture-
Initial days of programming were ruled by the assembly language which promoted powerful and easy to use instructions. This led the CPU designers to make instructions to do as much task as possible and provide every possible addressing modes for every instruction. Since, the earliest machines were programmed in assembly language and memory was slow and expensive. Due to slowness of memory accesses and the limited memory area, the designers were prompted to create instructions which could reduce the frequency of memory access. So, stress was given on the hardware part to implement functionality rather than in a memory constrained compiler. This finally encouraged dense and complex instructions in a microcode.
Characteristics of CISC architecture :-
- Complex Instruction decoding logic as in to accomplish the need of single-line instruction.
- Multiple addressing modes are supported by one instruction.
- Limited amount of chip space is required for General purpose registers.
- Special registers for stack pointer, interrupt handling, etc.
- Long instruction may extend beyond memory address boundaries.
- RISC architecture-
CISC was designed to bridge the semantic gap at most. Later on, experts realized that some high-level code couldn’t be represented by a machine level operation and would have to be compiled into sets of instructions. It turned out that even though the compilers were choosing the best instructions for the job at hand, the instructions still had too much overhead of unused features to execute quickly. Thus, RISC was the result of this semantic clash.
RISC uses small and highly optimized set of instructions. It is designed to perform at high speed because of simple instructions. RISC chips require fewer transistors, which makes them cheaper to design. Each instruction is of same length so as to fetch in a single operation. Most instructions complete in one machine cycle , which allows the processor to handle several instructions at same time. This is known as pipe lining.
Characteristics of RISC:-
- Limited fixed-length instructions to avoid any load/store and arithmetic combination in a single instruction.
- It supports simple data types and synthesize complex data types.
- Uses simple addressing modes.
- It contains large no. of registers to prevent frequent memory accesses.
- Pipe lining is supported because of fixed length instructions.
- It uses Harvard architecture i.e separate segments of data and instructions in memory.
Differences between RISC and CISC
There are lot of differences in terms of speed and level of complexity between both architectures. The major problem of RISC is the lack of widespread compatibility unlike CISC(x86 processors). The best area where RISC find its utility is in mobile and handheld devices(ARM architecture) i.e in embedded electronics. Intel and AMD develop CISC processors while Apple and SUN use RISC architecture. Many of today’s RISC chips support as many instructions as yesterday’s CISC chips.
Because a no. of advancements are used by both RISC and CISC processors, the demarcation between the two is getting diminished. The result of the convergence of these two is EPIC(explicitly Parallel Instruction Computing). EPIC based processors are used by Unisys and HP-Compaq.
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